//+-+-+-+-+
//|N|C|O|M|
//+-+-+-+-+---------------------------- Copyright 2009 scott a dixon [archxs] -+
//|                                                                            |
//| This file is part of the NanoCOM project <http://code.google.com/p/ncom/>. |
//|                                                                            |
//| Nano COM is free software: you can redistribute it and/or modify           |
//| it under the terms of the GNU Lesser General Public License as published   |
//| by the Free Software Foundation, either version 3 of the License, or       |
//| (at your option) any later version.                                        |
//|                                                                            |
//| Nano COM is distributed in the hope that it will be useful,                |
//| but WITHOUT ANY WARRANTY; without even the implied warranty of             |
//| MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the              |
//| GNU Lesser General Public License for more details.                        |
//|                                                                            |
//| You should have received a copy of the GNU General Public License          |
//| along with the Nano COM source.  If not, see                               |
//| <http://www.gnu.org/licenses/>.                                            |
//|                                                                            |
//+----------------------------------------------------------------------------+
#ifdef GNUNIX
#include "platform.h"

//+----------------------------------------------------------------------------+
//| ATOMIC OPERATIONS                                                          |
//+----------------------------------------------------------------------------+

//ASM REDUX
//
//AT&T syntax == "opcode src dst" versus Intel syntax == "opcode dst src"
//GCC prefixes registers with %
//opcode suffix chart:
// b == 8bit (byte)
// w == 16bit (word)
// l == 32bit (long)
// the "lock" keyword denotes atomicity
//+-----------------------------------+----------------------------------------+
//|       Intel Code                  |      AT&T Code                         |
//+-----------------------------------+----------------------------------------+
//| mov     eax,1                     |  movl    $1,%eax                       |
//| mov     ebx,0ffh                  |  movl    $0xff,%ebx                    |
//| int     80h                       |  int     $0x80                         |
//| mov     ebx, eax                  |  movl    %eax, %ebx                    |
//| mov     eax,[ecx]                 |  movl    (%ecx),%eax                   |
//| mov     eax,[ebx+3]               |  movl    3(%ebx),%eax                  |
//| mov     eax,[ebx+20h]             |  movl    0x20(%ebx),%eax               |
//| add     eax,[ebx+ecx*2h]          |  addl    (%ebx,%ecx,0x2),%eax          |
//| lea     eax,[ebx+ecx]             |  leal    (%ebx,%ecx),%eax              |
//| sub     eax,[ebx+ecx*4h-20h]      |  subl    -0x20(%ebx,%ecx,0x4),%eax     |
//+-----------------------------------+----------------------------------------+
//+---+--------------------+
//| r |    Register(s)     |
//+---+--------------------+
//| a |   %eax, %ax, %al   |
//| b |   %ebx, %bx, %bl   |
//| c |   %ecx, %cx, %cl   |
//| d |   %edx, %dx, %dl   |
//| S |   %esi, %si        |
//| D |   %edi, %di        |
//+---+--------------------+


/*
static __inline int ia64_atomic_add (int i, atomic_t *v)
{
    __s32 old, new;
    do {
        old = atomic_read(v);
        new = old + i;
    } while (ia64_cmpxchg(acq, v, old, new, sizeof(atomic_t)) != old);
    return new;
}*/

#endif

